This invention relates to a processing system of the kind including one or more processors and memory modules communicating by means of a multiple conductor bus.
The present invention is intended to have a particular utility in communications systems requiring data and circuit switching. Such systems, operating in real time, must operate very reliably. As the systems become progressively more complex, this requirement is increasingly more difficult to meet. For example, it is advantageous to design systems having multiple processors, including in some cases multiple processors accessing the same memory. It is often difficult to detect accurately the source of an error occurring in such a system, particularly if the error is intermittent. However, if errors are not detected and allowed to accummulate, the entire system may become involved, reaching a state from which recovery is impossible. In an application such as automatic funds transfer, it is highly undesirable for such an unrecoverable state to be reached.